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TPS23750EVM-107 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS23750EVM-107 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 12 page Board Layout www.ti.com 3.2 Bottom-Side Layout 3.3 Layout Considerations The layout of the PoE front end must use good practice for power and EMI/ESD. A basic set of recommendations include: • The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45 → Ethernet transformer → diode bridges → TVS and 0.1-mF capacitor → TPS23750 → bulk capacitor → converter input. • There should not be any crossovers of signals from one part of the flow to another. • All leads should be as short as possible with wide power traces and paired signal and return. • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output. • The TPS23750 should be located over split, local ground planes referenced to V SS for the PoE input and to RTN for the converter operation. Whereas the PoE side may operate without a ground plane, the converter side must have one. The PowerPad™ must be tied to the V SS plane or fill area, especially if power dissipation is a concern. Logic ground and power layers should not be present under the Ethernet input or the converter primary side. • Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay copper fills should be used in the power path. Converter layout benefits from basic rules such as: 1. Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses which include the power semiconductors and magnetics. 2. Reduce the length of all the traces in step 1. 3. Where possible, use vertical pairing. 4. Use the ground plane for the switching currents carefully. 5. Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside the power supply. 6. The current sensing on RSP/RSN is the most critical, noise-sensitive signal. It must be protected as in step 5, including exposure to the gate drive sign. 7. Pay special attention to spacing around the high-voltage sections of the converter. 8 TPS23750 Buck-Converter Evaluation Board – HPA107 SLVU136A – July 2005 – Revised January 2011 Submit Documentation Feedback © 2005–2011, Texas Instruments Incorporated |
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