UCC39571, UCC39572, UCC39573, UCC39574

SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

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APPLICATION INFORMATION

protection against a runaway charger

The use of a small N-channel level shifter (Q3 in the application diagrams) allows the IC to interface with the

high-side charge FET (Q1), even in the presence of a runaway charger. Only the drain-source voltage rating

of the charge FET limits the charge voltage that the protection circuit can withstand. The wakeup (WU) pin is

designed to handle input voltages greater than VDD, as long as the current is limited. In the examples shown,

the charge FET’s gate-source resistor (R1) provides this current limiting. Note that in Figure 2, a resistor and

zener (R2 and VR1) have been added to protect Q1 against any possibility of a voltage transient exceeding its

maximum gate-source rating.

overcurrent protection

The UCC3957 protects the battery pack from an overload or a hard short circuit using a two-tier overcurrent

protection scheme. The overcurrent protection is designed to go into a hiccup mode when the voltage drop

across an external-sense resistor (connected to the AN4 and BATLO pins) exceeds a certain threshold. In this

mode, the discharge FET is periodically turned off and on until the fault is removed. Once the fault is removed,

normal operation is automatically resumed.

To facilitate charging large capacitive loads, there are two overcurrent threshold voltages, each with its own

user-programmable time delay. This two-tier approach provides fast response to short circuits, while enabling

the battery pack to provide short-duration surge currents. It also facilitates the charging of large filter caps

without causing nuisance overcurrent trips.

The first-tier threshold is 150 mV nominal, corresponding to 6 A using a .025-

Ω sense resistor as shown in the

examples of Figure 1 and Figure 2. If the pack-discharge current exceeds this amount for a period of time,

determined by the capacitor on the CDLY1 pin, it then enters the hiccup mode. The first-tier hiccup duty cycle

is fixed at approximately 6%, minimizing power dissipation in the event of a sustained overload. The absolute

on and off times of the discharge FET (Q2) are controlled by the CDLY1 capacitor. A curve relating the delay

(on time) to this capacitor value is shown in Figure 4. The off time is approximately 17 times longer than the on

time.

The second-tier overcurrent threshold is nominally 375 mV, corresponding to 15 A using a .025-

Ω sense resistor.

If the pack current exceeds this value for a period of time, determined by the capacitor on the CDLY2 pin, it then

enters the hiccup-mode with a much lower duty cycle, typically less than 1%. The relationship of this time delay

(on time) to the CDLY2 capacitor value is shown in the curve of Figure 5. The off time during this hiccup mode

is still determined by the CDLY1 capacitor, as previously described. This technique greatly reduces the stress

and power dissipation in the FETs during short-circuit conditions.

In the examples shown in Figure 1 and Figure 2 (with CDLY1 = .022

µF), the first-tier overcurrent on time is

approximately 10 msec, while the off time is approximately 170 msec, resulting in a 5.9% duty cycle for currents

over 6 A (but less than 15 A). If no CDLY2 capacitor is used, the second-tier on time is less than 200

µsec

(assuming no stray capacitance), resulting in a duty cycle of about 0.1% for currents over 15 A. If CDLY2 = 22pF,

the typical on time for currents exceeding 15 A is approximately 800

µsec, resulting in a duty cycle of 0.5%.

Not Recommended for New Designs