Electronic Components Datasheet Search |
|
AD573JPZ Datasheet(PDF) 6 Page - Analog Devices |
|
AD573JPZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 10 page AD573 –6– CONTROL AND TIMING OF THE AD573 The operation of the AD573 is controlled by three inputs: CONVERT , HBE and LBE. Starting a Conversion The conversion cycle is initiated by a positive going CONVERT pulse at least 500 ns wide. The rising edge of this pulse resets the internal logic, clears the result of the previous conversion, and sets DR high. The falling edge of CONVERT begins the conversion cycle. When conversion is completed DR returns low. During the conversion cycle, HBE and LBE should be held high. If HBE or LBE goes low during a conversion, the data output buffers will be enabled and intermediate conversion re- sults will be present on the data output pins. This may cause bus conflicts if other devices in a system are trying to use the bus. tCS tDSC VOH + VOL 2 VIH + VIL 2 tC CONVERT DR Figure 9. Convert Timing Reading the Data The three-state data output buffers are enabled by HBE and LBE . Access time of these buffers is typically 150 ns (250 maxi- mum). The data outputs remain valid until 50 ns after the en- able signal returns high, and are completely into the high impedance state 100 ns later. VIH + VIL 2 LBE OR HBE tHD tDD VOH VOL DATA VALID tHL HIGH IMPEDANCE HIGH IMPEDANCE DB0–DB7 OR DB8–DB9 Figure 10. Read Timing TIMING SPECIFICATIONS (All grades, TA = TMIN–TMAX) Parameter Symbol Min Typ Max Units CONVERT Pulse Width tCS 500 – – ns DR Delay from CONVERT tDSC – 1 1.5 µs Conversion Time tC 10 20 30 µs Data Access Time tDD 0 150 250 ns Data Valid after HBE/LBE High tHD 50 – – ns Output Float Delay tHL – 100 200 ns MICROPROCESSOR INTERFACE CONSIDERATIONS— GENERAL When an analog-to-digital converter like the AD573 is inter- faced to a microprocessor, several details of the interface must be considered. First, a signal to start the converter must be gen- erated; then an appropriate delay period must be allowed to pass before valid conversion data may be read. In most applications, the AD573 can interface to a microprocessor system with little or no external logic. The most popular control signal configuration consists of de- coding the address assigned to the AD573, then gating this sig- nal with the system’s WR signal to generate the CONVERT pulse, and gating it with RD to enable the output buffers. The use of a memory address and memory WR and RD signals de- notes “memory-mapped” I/O interfacing, while the use of a separate I/O address space denotes “isolated I/O” interfacing. In 8-bit bus systems, the 10-bit AD573 will occupy two locations when data is to be read; therefore, two (usually consecutive) ad- dresses must be decoded. One of the addresses can also be used as the address which produces the CONVERT signal during WR operations. Figure 11 shows a generalized diagram of the control logic for an AD573 interfaced to an 8-bit data bus, where two addresses (ADC ADDR and ADC ADDR + 1) have been decoded. ADC ADDR starts the converter when written to (the actual data be- ing written to the converter does not matter) and contains the high byte data during read operations. ADC ADDR + 1 per- forms no function during write operations, but contains the low byte data during read operations. Figure 11. General AD573 Interface to 8-Bit Microprocessor In systems where this read-write interface is used, at least 30 microseconds (the maximum conversion time) must be allowed to pass between starting a conversion and reading the results. This delay or “timeout” period can be implemented in a short software routine such as a countdown loop, enough dummy in- structions to consume 30 microseconds, or enough actual useful instructions to consume the required time. In tightly-timed sys- tems, the DR line may be read through an external three-state buffer to determine precisely when a conversion is complete. Higher speed systems may choose to use DR to signal an inter- rupt to the processor at the end of a conversion. Figure 12. Typical AD573 Interface Timing Diagram REV. B |
Similar Part No. - AD573JPZ |
|
Similar Description - AD573JPZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |