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AD5165BUJZ100 Datasheet(PDF) 4 Page - Analog Devices

Part # AD5165BUJZ100
Description  256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5165BUJZ100 Datasheet(HTML) 4 Page - Analog Devices

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AD5165
Rev. 0 | Page 4 of 16
TIMING CHARACTERISTICS—100 kΩ VERSION
VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
3-WIRE INTERFACE TIMING CHARACTERISTICS2, ,3 4 (specifications apply to all parts)
Clock Frequency
fCLK= 1/( tCH+ tCL)
25
MHz
Input Clock Pulse Width
tCH, tCL
Clock level high or low
20
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CS Setup Time
tCSS
15
ns
CS Low Pulse Width
tCSW
40
ns
CLK Fall to CS Rise Hold Time
tCSH0
0
ns
CLK Fall to CS Fall Hold Time
tCSH1
0
ns
CS Fall to Clock Rise Setup
tCS1
10
ns
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 All dynamic characteristics use VDD = 5 V.
4 See
and
for location of measured values. All input control voltages are specified with t
Figure 34
Figure 35
R
= tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.


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