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AD8304ARU-REEL Datasheet(PDF) 9 Page - Analog Devices |
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AD8304ARU-REEL Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page REV. A AD8304 –9– To repeat the previous example: for a reference power level of 1 mW, a POPT of 3 mW would correspond to a DOPT of 10 log10(3) = 4.77 dBm, while the equivalent intercept power of 110 pW will correspond to a DZ of –69.6 dBm; now using Equation 8: VmV V LOG = {} = 20 4 77 69 9 1 487 . – (– .) . (9) which is in agreement with the result from Equation 7. GENERAL STRUCTURE The AD8304 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique translinear log amp. Figure 1 is a simplified schematic showing the key elements. PHOTODIODE INPUT CURRENT IPD INPT ~10k C1 R1 VNEG (NORMALLY GROUNDED) IREF (INTERNAL) 0.5V Q1 Q2 QM INTERCEPT AND TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T K) VSUM 0.6V 0.5V 0.5V VBE1 VBE2 200 VPDB VPDB VBE1 VBE2– 296mVP ACOM VLOG VLOG 40 A/dec 5k Figure 1. Simplified Schematic The photodiode current IPD is received at input Pin INPT. The summing voltage at this node is essentially equal to that on the two adjacent guard pins, VSUM, due to the low offset voltage of the ultralow bias J-FET op amp used to support the operation of the transistor Q1, which converts the current to a logarithmic voltage, as delineated in Equation 1. VSUM is needed to provide the collector-emitter bias for Q1, and is internally set to 0.5 V, using a quarter of the reference voltage of 2 V appearing on Pin VREF. In conventional translinear log amps, the summing node is gener- ally held at ground potential, but that condition is not readily realized in a single-supply part. To address this, the AD8304 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. For a VN of at least –0.5 V the summing node can be connected to ground potential. Larger negative voltages may be used, with essentially no effect on scaling, up to a maximum supply of 8 V between VPOS and VNEG. Note that the resistance at the VSUM pins is approximately 10 k Ω to ground; this voltage is not intended as a general bias source. The input-dependent VBE of Q1 is compared with the fixed VBE of a second transistor, Q2, which operates at an accurate internally generated current, IREF = 10 µA. The overall intercept is arranged to be 100,000 times smaller than IREF, in later parts of the signal chain. The difference between these two VBE values can be written as VV kT qI I BE BE PD REF 12 – / log ( / ) = 10 (10) Thus, the uncertain and temperature-dependent saturation current, IS that appears in Equation 1, has been eliminated. Next, to eliminate the temperature variation of kT/q, this difference voltage is applied to a processing block—essentially an analog divider that effectively puts a variable proportional to temperature underneath the T in Equation 10. In this same block, IREF is trans- formed to the much smaller current IZ, to provide the previously defined value for VLOG, that is, VV I I LOG Y PD Z = log ( / ) 10 (11) Recall that VY is 200 mV/decade and IZ is 100 pA. Internally, this is generated first as an output current of 40 µA/decade (2 µA/dB) applied to an internal load resistor from VLOG to ACOM that is laser-trimmed to 5 k Ω ±1%. The slope may be altered at this point by adding an external shunt resistor. This is required when using the minimum supply voltage of 3.0 V, because the span of VLOG for the full 160 dB (eight-decade) range of IPD amounts to 8 0.2 V = 1.6 V, which exceeds the internal headroom at this node. Using a shunt of 5 k Ω, this is reduced to 800 mV, that is, the slope becomes 5 mV/dB. In those applications needing a higher slope, the buffer can provide voltage gain. For example, to raise the output swing to 2.4 V, which can be accommodated by the rail-to-rail buffer when using a 3.0 V supply, a gain of 3 can be used which raises the slope to 15 mV/dB. Slope variations implemented in these ways do not affect the intercept. Keep in mind these measures to address the limitations of a small positive supply voltage will not be needed when IPD is limited to about 1 mA maximum. They can also be avoided by using a negative supply that allows VLOG to run below ground, which will be discussed later. Figure 1 shows how a sample of the input current is derived using a very small monitoring transistor, QM, connected in parallel with Q1. This is used to generate the photodiode bias, VPDB, at Pin VPDB, which varies from 0.6 V when IPD = 100 pA, and reverse-biases the diode by 0.1 V (after subtracting the fixed 0.5 V at INPT) and rises to 2.6 V at IPD = 10 mA, for a net diode bias of 2 V. The driver for this output is current-limited to about 20 mA. The system is completed by the final buffer amplifier, which is essentially an uncommitted op amp with a rail-to-rail output capability, a 10 MHz bandwidth, and good load-driving capabili- ties, and may be used to implement multipole low-pass filters, and a voltage reference for internal use in controlling the scaling, but that is also made available at the 2.0 V level at Pin VREF. Figure 2 shows the ideal output VLOG versus IPD. Bandwidth and Noise Considerations The response time and wide-band noise of translinear log amps are fundamentally a function of the signal current IPD. The bandwidth becomes progressively lower as IPD is reduced, largely due to the effects of junction capacitances in Q1. This is easily understood by noting that the transconductance (gm) of a bipolar transistor is a linear function of collector current, IC, (hence, translinear), which in this case is just IPD. The corre- sponding incremental emitter resistance is: r kT qI e PD == 1 g m (12) Basically, this resistance and the capacitance CJ of the transistor generate a time constant of reCJ and thus a corresponding low-pass corner frequency of: f qI kTC dB PD j 3 2 = π (13) showing the proportionality of bandwidth to current. |
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