AD9523-1BCPZ datasheet(10/60 Pages) AD

Part #	AD9523-1BCPZ

Description	Low Jitter Clock Generator

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AD9523-1

Rev. B | Page 10 of 60

STATUS OUTPUT PINS—STATUS1, STATUS0

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Output High

2.94

V

Output Low

0.4

V

SERIAL CONTROL PORT—SPI MODE

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 40 kΩ pull-up resistor

Voltage

Input Logic 1

2.0

V

Input Logic 0

0.8

V

Current

Input Logic 1

30

μA

Input Logic 0

−110

μA

The minus sign indicates that, due to the

internal pull-up resistor, current is flowing out

of the AD9523-1

Input Capacitance

2

pF

SCLK (INPUT) IN SPI MODE

SCLK has an internal 40 kΩ pull-down resistor

in SPI mode but not in I2C mode

Voltage

Input Logic 1

2.0

V

Input Logic 0

0.8

V

Current

Input Logic 1

240

μA

Input Logic 0

1

μA

Input Capacitance

2

pF

SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)

Voltage

Input Logic 1

2.0

V

Input Logic 0

0.8

V

Current

Input Logic 1

1

μA

Input Logic 0

1

μA

Input Capacitance

2

pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

V

Output Logic 0 Voltage

0.4

V

TIMING

Clock Rate (SCLK, 1/tSCLK)

25

MHz

Pulse Width High, tHIGH

8

ns

Pulse Width Low, tLOW

12

ns

SDIO to SCLK Setup, tDS

3.3

ns

SCLK to SDIO Hold, tDH

0

ns

SCLK to Valid SDIO and SDO, tDV

14

ns

CS to SCLK Setup, tS

10

ns

CS to SCLK Setup and Hold, tS, tC

0

ns

CS Minimum Pulse Width High, tPWH

6

ns

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AD9523-1BCPZ Datasheet(PDF) 10 Page - Analog Devices

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