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AD9639BCPZ-170 Datasheet(PDF) 6 Page - Analog Devices |
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AD9639BCPZ-170 Datasheet(HTML) 6 Page - Analog Devices |
6 / 36 page AD9639 Data Sheet Rev. B | Page 6 of 36 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 4. AD9639BCPZ-170 AD9639BCPZ-210 Parameter1 Temp Min Typ Max Min Typ Max Unit CLOCK Clock Rate Full 100 170 100 210 MSPS Clock Pulse Width High (tEH) Full 2.65 2.9 2.15 2.4 ns Clock Pulse Width Low (tEL) Full 2.65 2.9 2.15 2.4 ns DATA OUTPUT PARAMETERS Data Output Period or UI (DOUT + x, DOUT − x) Full 1/(20 × fCLK) 1/(20 × fCLK) Seconds Data Output Duty Cycle 25°C 50 50 % Data Valid Time 25°C 0.8 0.8 UI PLL Lock Time (tLOCK) 25°C 4 4 µs Wake-Up Time (Standby) 25°C 250 250 ns Wake-Up Time (Power-Down)2 25°C 50 50 μs Pipeline Latency Full 40 40 CLK cycles Data Rate per Channel (NRZ) 25°C 3.4 4.2 Gbps Deterministic Jitter 25°C 10 10 ps Random Jitter 25°C 6 6 ps rms Channel-to-Channel Bit Skew 25°C 0 0 Seconds Channel-to-Channel Packet Skew3 25°C ±1 ±1 CLK cycles Output Rise/Fall Time 25°C 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25°C 100 100 Ω APERTURE Aperture Delay (tA) 25°C 1.2 1.2 ns Aperture Uncertainty (Jitter) 25°C 0.2 0.2 ps rms OUT-OF-RANGE RECOVERY TIME 25°C 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Receiver dependent. 3 See the Serial Data Frame section. |
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