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ADG729BRU Datasheet(PDF) 5 Page - Analog Devices

Part # ADG729BRU
Description  CMOS, Low Voltage, 2-Wire Serially Controlled, Matrix Switches
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADG729BRU Datasheet(HTML) 5 Page - Analog Devices

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ADG728/ADG729
–5–
PIN FUNCTION DESCRIPTIONS
ADG728
ADG729
Mnemonic
Function
1
1
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into
the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated
with this 2-wire serial interface.
2
RESET
Active low control input that clears the input register and turns all switches to the
OFF condition.
3
3
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into
the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cycle. It is a bidirectional open-drain data line which should be
pulled to the supply with an external pull-up resistor.
4, 5, 6, 7
4, 5, 6, 7
Sxx
Source. May be an input or output.
8
8, 9
Dx
Drain. May be an input or output.
9, 10, 11, 12
10, 11, 12, 13
Sxx
Source. May be an input or output.
13
14
VDD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
14
15
GND
Ground Reference.
15
2
A1
Address Input. Sets the second least significant bit of the 7-bit slave address.
16
16
A0
Address Input. Sets the least significant bit of the 7-bit slave address.
ADG729
SCL
S2A
S3A
S4A
S1A
DA
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1
GND
VDD
SDA
ADG729
A0
S2B
S3B
S4B
S1B
DB
ADG728
SCL
RESET
S2
S3
S4
S1
D
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1
S5
S6
S7
GND
VDD
S8
SDA
ADG728
A0
PIN CONFIGURATIONS
REV. C


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