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ADG729BRU-REEL Datasheet(PDF) 4 Page - Analog Devices |
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ADG729BRU-REEL Datasheet(HTML) 4 Page - Analog Devices |
4 / 13 page ADG728/ADG729 –4– REV. C TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V. All specifications −40°C to +85°C, unless otherwise noted. See Figure 1. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments fSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min SCL high time, tHIGH t3 1.3 µs min SCL low time, tLOW t4 0.6 µs min Start/repeated start condition hold time, tHD, STA t5 100 ns min Data setup time, tSU, DAT t61 0.9 µs max Data hold time, tHD, DAT 0 µs min t7 0.6 µs min Setup time for repeated start, tSU, STA t8 0.6 µs min Stop condition setup time, tSU, STO t9 1.3 µs min Bus free time between a stop condition and a start condition, tBUF t10 300 ns max Rise time of both SCL and SDA when receiving, tR 20 + 0.1Cb2 ns min t11 250 ns max Fall time of SDA when receiving, tF 300 ns max Fall time of SDA when transmitting, tF 0.1Cb2 ns min Cb2 400 pF max Capacitive load for each bus line tSP3 50 ns max Pulse width of spike suppressed 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 2 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. t3 t2 t1 t4 t8 t6 t5 t9 t7 t4 t11 t10 SDA SCL START CONDITION START CONDITION REPEATED START CONDITION STOP CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram |
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