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ADSP-BF592BCPZ-2 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-BF592BCPZ-2 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 44 page  Rev. B | Page 10 of 44 | July 2013 ADSP-BF592 recommended. The two capacitors and the series resistor shown in Figure 4 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 4 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in Figure 4. A design procedure for third-overtone oper- ation is discussed in detail in (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices web- site (www.analog.com)—use site search on “EE-168.” The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 5, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable 5× to 64× multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 6×, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. The maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT and VDDEXT; the VCO is always permitted to run up to the frequency speci- fied by the part’s instruction rate. The EXTCLK pin can be configured to output either the SCLK frequency or the input buffered CLKIN frequency, called CLKBUF. When configured to output SCLK (CLKOUT), the EXTCLK pin acts as a refer- ence signal in many timing specifications. While three-stated by default, it can be enabled using the VRCTL register. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 4 illustrates typical system clock ratios. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 5. This programmable core clock capability is useful for fast core frequency modifications. The maximum CCLK frequency both depends on the part’s instruction rate (see Ordering Guide) and depends on the applied VDDINT voltage. See Table 8 for details. The maximal sys- tem clock rate (SCLK) depends on the chip package and the applied VDDINT and VDDEXT voltages (see Table 10). Figure 4. External Crystal Connections CLKIN CLKOUT (SCLK) XTAL SELECT CLKBUF TO PLL CIRCUITRY FOR OVERTONE OPERATION ONLY: NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 . 18 pF * EN 18 pF * 330 * BLACKFIN 560 EXTCLK EN Figure 5. Frequency Modification Methods Table 4. Example System Clock Ratios Signal Name SSEL3–0 Divider Ratio VCO/SCLK Example Frequency Ratios (MHz) VCO SCLK 0010 2:1 100 50 0110 6:1 300 50 1010 10:1 400 40 Table 5. Core Clock Ratios Signal Name CSEL1–0 Divider Ratio VCO/CCLK Example Frequency Ratios (MHz) VCO CCLK 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 PLL 5 to 64 ÷ 1 to 15 ÷ 1, 2, 4, 8 VCO CLKIN “FINE” ADJUSTMENT REQUIRES PLL SEQUENCING “COARSE” ADJUSTMENT ON-THE-FLY CCLK SCLK SCLK CCLK |
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