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ICL7660CBAZA Datasheet(PDF) 9 Page - Intersil Corporation |
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ICL7660CBAZA Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 11 page 9 FN3072.7 October 10, 2005 every cycle. In a typical application where fOSC = 10kHz and C = C1 = C2 = 10µF: RO ≅ 46 + 20 + 5 (ESRC) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(fPUMP • C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10 Ω. RO/ ≅ 46 + 20 + 5 (ESRC) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(fPUMP • C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10 Ω. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2 voltages, A and B, as shown in Figure 14. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flow into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 • IOUT, hence the total drop is 2• IOUT • eSRC2V. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current to the load. The drop at B is lOUT • t2/C2V. The peak-to-peak ripple voltage is the sum of these voltage drops: Again, a low ESR capacitor will reset in a higher performance output. Paralleling Devices Any number of ICL7660 and ICL7660A voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: Cascading Devices The ICL7660 and ICL7660A may be cascaded as shown to produced larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = -n (VIN), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660 and ICL7660A ROUT values. Changing the ICL7660/ICL7660A Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 17. In order to prevent possible device latchup, a 1k Ω resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k Ω pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive-going edge of the clock. It is also possible to increase the conversion efficiency of the ICL7660 and ICL7660A at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 18. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC) and V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10µF to 100µF). RO ≅ 2 (23) + 1 + 4 (ESRC1) + ESRC2 (5 • 103) (10-5) RO ≅ 2 (23) + 1 + 4 (ESRC1) + ESRC2 (5 • 103) (10-5) VRIPPLE ≅ [ 1 + 2 (ESRC2) ]I OUT 2 (fPUMP) (C2) ROUT = ROUT (of ICL7660/ICL7660A) n (number of devices) 1 2 3 4 8 7 6 5 + - 10 µF ICL7660 VOUT V+ + - 10 µF V+ CMOS GATE 1k Ω ICL7660A FIGURE 17. EXTERNAL CLOCKING ICL7660, ICL7660A |
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