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AM1705BPTP4 Datasheet(PDF) 1 Page - Texas Instruments

Part # AM1705BPTP4
Description  AM1705 ARM Microprocessor
Download  164 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM1705BPTP4 Datasheet(HTML) 1 Page - Texas Instruments

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AM1705
www.ti.com
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
AM1705 ARM Microprocessor
Check for Samples: AM1705
1
AM1705 ARM Microprocessor
1.1
Features
123
– 8 Quick DMA Channels
• Highlights
– Programmable Transfer Burst Size
– 375/456-MHz ARM926EJ-S™ RISC Core
• 128K-Byte RAM Memory
– ARM9 Memory Architecture
• 3.3V LVCMOS IOs (except for USB Interface)
– Programmable Real-Time Unit Subsystem
• Two External Memory Interfaces:
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– EMIFA
– Two External Memory Interfaces
NOR (8-Bit-Wide Data)
– Three Configurable 16550 type UART
NAND (8-Bit-Wide Data)
Modules
– EMIFB
– Two Serial Peripheral Interfaces (SPI)
16-Bit SDRAM With 128MB Address
– Multimedia Card (MMC)/Secure Digital (SD)
Space
Card Interface with Secure Data I/O (SDIO)
• Three Configurable 16550 type UART Modules:
– Two Master/Slave Inter-Integrated Circuit
– UART0 With Modem Control Signals
– USB 2.0 OTG Port With Integrated PHY
– 16-byte FIFO
– Two Multichannel Audio Serial Ports
– 16x or 13x Oversampling Option
– 10/100 Mb/s Ethernet MAC (EMAC)
– Autoflow control signals (CTS, RTS) on
– One 64-Bit General-Purpose Timer
UART0 only
– One 64-bit General-Purpose/Watchdog Timer
• Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
– Three Enhanced Pulse Width Modulators
• Programmable Real-Time Unit Subsystem
– Three 32-Bit Enhanced Capture Modules
(PRUSS)
• Applications
– Two Independent Programmable Realtime
– Industrial Automation
Unit (PRU) Cores
– Home Automation
32-Bit Load/Store RISC architecture
– Test and Measurement
4K Byte instruction RAM per core
– Portable Data Terminals
512 Bytes data RAM per core
– Educational Consoles
PRU Subsystem (PRUSS) can be disabled
– Power Protection Systems
via software to save power
• 375/456-MHz ARM926EJ-S™ RISC Core
– Standard power management mechanism
– 32-Bit and 16-Bit (Thumb®) Instructions
Clock gating
– Single Cycle MAC
Entire subsystem under a single PSC
– ARM™Jazelle® Technology
clock gating domain
– EmbeddedICE-RT™ for Real-Time Debug
– Dedicated interrupt controller
• ARM9 Memory Architecture
– Dedicated switched central resource
– 16K-Byte Instruction Cache
• Multimedia Card (MMC)/Secure Digital (SD)
– 16K-Byte Data Cache
Card Interface with Secure Data I/O (SDIO)
– 8K-Byte RAM (Vector Table)
• Two Master/Slave Inter-Integrated Circuit (I2C
– 64K-Byte ROM
Bus™)
• Enhanced Direct-Memory-Access Controller 3
• USB 2.0 OTG Port With Integrated PHY (USB0)
(EDMA3):
– USB 2.0 Full-Speed Client
– 2 Transfer Controllers
– USB 2.0 Full-/Low-Speed Host
– 32 Independent DMA Channels
– End Point 0 (Control)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM926EJ-S, ETM9, CoreSight are trademarks of ARM Limited.
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2010–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.


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