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TMS370C150A Datasheet(PDF) 8 Page - Texas Instruments |
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TMS370C150A Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 75 page  TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 modes (continued) – Reduces external interface decode logic by using the precoded chip select outputs that provide direct memory/peripheral chip select or chip enable functions. – Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2, CSH1, CSH2, and CSH3 as memory-bank selects under software control. – Function B maps up to 40K bytes of external memory into the address space by using EDS under software control. D Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations. D Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external bus interface. – Application program in external memory enables the internal program ROM or EPROM to be active in the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control register accomplishes this.) memory/peripheral wait operation The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT-input pin. The CPU continues to wait as long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller. Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions and memory and peripheral accesses automatically, thus making every external access a minimum of three system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states can be used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost. |
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