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UCD9244RGCT Datasheet(PDF) 6 Page - Texas Instruments

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Part # UCD9244RGCT
Description  Digital PWM System Controller with 4-bit, 6-bit, or 8-bit VID Support
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UCD9244RGCT Datasheet(HTML) 6 Page - Texas Instruments

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UCD9244
SLVSAL6A
– NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
PARAMETER
TEST CONDITIONS
MAX TIME
UNIT
Time to disable DPWM output base on active FAULT pin
tFAULT
High level on FAULT pin
18
µs
signal
Time to disable the DPWM A output based on internal
Switch
tCLF
Step change in CS voltage from 0V to 2.5V
4
analog comparator
Cycles
PMBUS/SMBUS/I
2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus are shown below.
Figure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram
I
2C/SMBus/PMBus TIMING REQUIREMENTS
TA = –40°C to 125°C, 3V < V33 < 3.6V, typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSMB
SMBus/PMBus operating frequency
Slave mode; SMBC 50% duty cycle
10
1000
kHz
fI2C
I C operating frequency
Slave mode; SCL 50% duty cycle
10
1000
kHz
t(BUF)
Bus free time between start and stop
4.7
µs
t(HD:STA)
Hold time after (repeated) start
0.26
µs
t(SU:STA)
Repeated start setup time
0.26
µs
t(SU:STO)
Stop setup time
0.26
µs
t(HD:DAT)
Data hold time
Receive mode
0
ns
t(SU:DAT)
Data setup time
50
ns
t(TIMEOUT)
Error signal/detect
See (1)
35
ms
t(LOW)
Clock low period
0.5
µs
t(HIGH)
Clock high period
See (2)
0.26
50
µs
t(LOW:SEXT) Cumulative clock low slave extend time See
(3)
25
ms
tFALL
Clock/data fall time
Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15)
1000
ns
tRISE
Clock/data rise time
Fall time tFALL = 0.9 V33 to (VILMAX – 0.15)
1000
ns
(1)
The UCD9244 times out when any clock low exceeds t(TIMEOUT).
(2)
t(HIGH) , max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9244 that is
in progress.
(3)
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
6
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© 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :UCD9244


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