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HN85C256AFPI10E Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HN85C256AFPI10E Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 18 page HN58C256AI Series R10DS0218EJ0100 Rev.1.00 Page 10 of 16 Oct 07, 2013 Data Polling Timing Waveform t CE t OEH t WC t DW t OES Address CE WE OE I/O7 t OE Din X An An Dout X Dout X *9 *9 An Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle bit Waveform Notes: 1. I/O6 beginning state is "1". 2. I/O6 ending state will vary. 3. See AC read characteristics. 4. Any address location can be used, but the address must be fixed. WE t OES OE CE Dout I/O6 Dout Dout Dout Next mode t OE t CE t DW t WC t OEH *1 *2 *2 Address *3 *3 *4 Din |
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