RMLV0408E Series

Preliminary

R10DS0217EJ0001 Rev.0.01

Page 10 of 10

2013.09.10

Parameter

Symbol

Min.

Typ.

Max.

Unit

Test conditions

*24

1.5

─

─

V

Vin ≥ 0V,

Data retention current

─

0.4

*23

2

A

~+25°C

CS# ≥ Vcc-0.2V

─

─

3

A

~+40°C

─

─

5

A

~+70°C

─

─

7

A

~+85°C

Chip deselect time to data retention

0

─

─

ns

See retention waveform.

Operation recovery time

5

─

─

ms

Note 23. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.

24. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin

levels (address, WE#, OE#, I/O) can be in the high-impedance state.

Low Vcc Data Retention Timing Waveforms (CS# controlled)

CS#

CS# Controlled

2.7V

2.7V

2.2V

2.2V