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IA82510PLC28IR2 Datasheet(PDF) 10 Page - InnovASIC, Inc |
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IA82510PLC28IR2 Datasheet(HTML) 10 Page - InnovASIC, Inc |
10 / 25 page IA82510 Data Sheet Asynchronous Serial Controller February 25, 2011 IA211001219-05 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 10 of 25 1-888-824-4184 ® 3. Functional Overview 3.1 Transmitter The Transmit function consists of a 4 11 bit FIFO, and a Transmit Engine. The 4 11 FIFO is configurable as any depth between one and four words inclusive. The transmit engine is responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin. The transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. Transmit Communication parameters that can be programmed include: Parity modes Stop Bits Character Length FIFO Depth Clocking Options RTS and CTS modes For more details, see Section 3.4, Register Description. 3.2 Receiver The Receiver function consists of a 4 11 configurable FIFO and a Receive Engine. The receive engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing the data in the FIFO. The receive engine is highly configurable with parameters that include: Parity modes Stop Bits Character Length FIFO Depth Clocking Options Address Matching Options Control Character Detection RTS and CTS modes For more details, see Section 3.4, Register Description. 3.3 Bus Interface The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read and write the IA82510 Registers. It consists of the following I/O lines: |
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