TLV5624

2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS235B − JULY 1999 − REVISED APRIL 2004

5

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electrical characteristics over recommended operating conditions (unless otherwise noted)

(Continued)

reference pin configured as input (REF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VI

Input voltage

0

VDD−1.5

V

RI

Input resistance

10

M

Ω

CI

Input capacitance

5

pF

Reference input bandwidth

REF = 0.2 Vpp + 1.024 V dc

Fast

1.3

MHz

Reference input bandwidth

REF = 0.2 Vpp + 1.024 V dc

Slow

525

kHz

Reference feedthrough

REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)

−80

dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = VDD

1

µA

IIL

Low-level digital input current

VI = 0 V

−1

µA

Ci

Input capacitance

8

pF

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ts(FS)

Output settling time, full scale

RL = 10 kΩ,CL = 100 pF,

Fast

1

3

s

ts(FS)

Output settling time, full scale

RL = 10 kΩ,CL = 100 pF,

See Note 11

Slow

3.5

7

µs

ts(CC)

Output settling time, code to code

RL = 10 kΩ,CL = 100 pF,

Fast

0.5

1.5

s

ts(CC)

Output settling time, code to code

RL = 10 kΩ,CL = 100 pF,

See Note 12

Slow

1

2

µs

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

Fast

8

V/ s

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

See Note 13

Slow

1.5

V/

µs

Glitch energy

DIN = 0 to 1,

fCLK = 100 kHz,

CS = VDD

5

nV−S

SNR

Signal-to-noise ratio

53

57

S/(N+D)

Signal-to-noise + distortion

fs = 480 kSPS, fout = 1 kHz,

48

47

dB

THD

Total harmonic distortion

fs = 480 kSPS, fout = 1 kHz,

RL = 10 kΩ,CL = 100 pF

−50

−48

dB

Spurious free dynamic range

RL = 10 k ,CL = 100 pF

50

62

NOTES: 11. Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within

± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.