©1995 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74LCX00 Rev. 1.7.0

9

Physical Dimensions

Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8

°

0

°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45

°

1

0.10

C

C

B

C

A

7

M

14

B

A

8

SEE DETAIL A

5.60

0.65

1.70

1.27

8.75

8.50

7.62

6.00

4.00

3.80

(0.33)

1.27

0.51

0.35

1.75 MAX

1.50

1.25

0.25

0.10

0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

R0.10

0.50

0.25