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AD9739 Datasheet(PDF) 6 Page - Analog Devices |
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AD9739 Datasheet(HTML) 6 Page - Analog Devices |
6 / 48 page AD9739 Data Sheet Rev. B | Page 6 of 48 SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3. Parameter Min Typ Max Unit WRITE OPERATION (See Figure 36) SCLK Clock Rate, fSCLK (or /tSCLK) 20 MHz SCLK Clock High, tHI 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS 3 ns SCLK to CS Hold Time, tH 2 ns READ OPERATION (See Figure 37 and Figure 38) SCLK Clock Rate, fSCLK (or /tSCLK) 20 MHz SCLK Clock High, tHI 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS 3 ns SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns CS to SDIO (or SDO) Output Valid to High-Z, tEZ 2 ns INPUTS (SDIO, SCLK, CS) Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, IIH −10 +10 μA Current in Low, IIL −10 +10 μA OUTPUT (SDIO) Voltage Out High, VOH 2.4 3.5 V Voltage Out Low, VOL 0 0.4 V Current Out High, IOH 4 mA Current Out Low, IOL 4 mA |
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