 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-BF608 Datasheet(PDF) 10 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-BF608 Datasheet(HTML) 10 Page - Analog Devices |
|
|
10 / 112 page  Rev. 0 | Page 10 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 • A 32-bit threshold block with 16 thresholds, a histogram, and run-length encoding • Two 32-bit integral blocks that support regular and diago- nal integrals • An up- and down-scaling unit with independent scaling ratios for horizontal and vertical components • Input and output formatters for compatibility with many data formats, including Bayer input format The PVP can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form different pipeline structures. The PVP supports the simultaneous processing of up to four data streams. The memory pipe stream operates on data received by DMA from any L1, L2, or L3 memory. The three camera pipe streams operate on a common input received directly from any of the three PPI inputs. Optionally, the PIXC can convert color data received by the PPI and forward luma values to the PVP’s monochrome engine. Each stream has a dedicated DMA output. This preprocessing concept ensures careful use of available power and bandwidth budgets and frees up the processor cores for other tasks. The PVP provides for direct core MMR access to all control/sta- tus registers. Two hardware interrupts interface to the system event controller. For optimal performance, the PVP allows reg- ister programming through its control DMA interface, as well as outputting selected status registers through the status DMA interface. This mechanism enables the PVP to automatically process job lists completely independent of the Blackfin cores. Pixel Compositor (PIXC) The pixel compositor (PIXC) provides image overlays with transparent-color support, alpha blending, and color space con- version capabilities for output to TFT LCDs and NTSC/PAL video encoders. It provides all of the control to allow two data streams from two separate data buffers to be combined, blended, and converted into appropriate forms for both LCD panels and digital video outputs. The main image buffer pro- vides the basic background image, which is presented in the data stream. The overlay image buffer allows the user to add multiple foreground text, graphics, or video objects on top of the main image or video data stream. Parallel Peripheral Interface (PPI) The processor provides up to three parallel peripheral interfaces (PPIs), supporting data widths up to 24 bits. The PPI supports direct connection to TFT LCD panels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and other general-purpose peripherals. The following features are supported in the PPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. • Various framed, non-framed, and general-purpose operat- ing modes. Frame syncs can be generated internally or can be supplied by an external device. • ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decode. • Optional packing and unpacking of data to/from 32 bits from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is enabled, endianness can be configured to change the order of packing/unpacking of bytes/words. • RGB888 can be converted to RGB666 or RGB565 for trans- mit modes. •Various de-interleaving/interleaving modes for receiv- ing/transmitting 4:2:2 YCrCb data. •Configurable LCD data enable (DEN) output available on Frame Sync 3. PROCESSOR SAFETY FEATURES The ADSP-BF60x processor has been designed for functional safety applications. While the level of safety is mainly domi- nated by the system concept, the following primitives are provided by the devices to build a robust safety concept. Dual Core Supervision The processor has been implemented as dual-core devices to separate critical tasks to large independency. Software models support mutual supervision of the cores in symmetrical fashion. Multi-Parity-Bit-Protected L1 Memories In the processor’s L1 memory space, whether SRAM or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. This applies both to L1 instruction and data memory spaces. ECC-Protected L2 Memories Error correcting codes (ECC) are used to correct single event upsets. The L2 memory is protected with a Single Error Correct- Double Error Detect (SEC-DED) code. By default ECC is enabled, but it can be disabled on a per-bank basis. Single-bit errors are transparently corrected. Dual-bit errors can issue a system event or fault if enabled. ECC protection is fully trans- parent to the user, even if L2 memory is read or written by 8-bit or 16-bit entities. CRC-Protected Memories While parity bit and ECC protection mainly protect against ran- dom soft errors in L1 and L2 memory cells, the CRC engines can be used to protect against systematic errors (pointer errors) and static content (instruction code) of L1, L2 and even L3 memo- ries (DDR2, LPDDR). The processors feature two CRC engines which are embedded in the memory-to-memory DMA control- lers. CRC check sums can be calculated or compared on the fly during memory transfers, or one or multiple memory regions can be continuously scrubbed by single DMA work unit as per DMA descriptor chain instructions. The CRC engine also pro- tects data loaded during the boot process. |
Similar Part No. - ADSP-BF608 |
|
Similar Description - ADSP-BF608 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
