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AD5291BRUZ-50-RL7 Datasheet(PDF) 11 Page - Analog Devices |
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AD5291BRUZ-50-RL7 Datasheet(HTML) 11 Page - Analog Devices |
11 / 32 page AD5291/AD5292 Rev. D | Page 11 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET VSS A W RDY SYNC VLOGIC SCLK B VDD EXT_CAP 1 2 3 4 5 6 7 DIN GND 14 13 12 11 10 9 8 AD5291/ AD5292 TOP VIEW Not to Scale SDO Figure 5. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. 2 VSS Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 3 A Terminal A of RDAC. VSS ≤ VA ≤ VDD. 4 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. 5 B Terminal B of RDAC. VSS ≤ VB ≤ VDD. 6 VDD Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 7 EXT_CAP External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. 8 VLOGIC Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 9 GND Ground Pin, Logic Ground Reference. 10 DIN Serial Data Input. The AD5291 and AD5292 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 11 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 12 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. 13 SDO Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. 14 RDY Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory. |
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