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AD7392ARZ-REEL Datasheet(PDF) 4 Page - Analog Devices |
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AD7392ARZ-REEL Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD7392/AD7393 Rev. C | Page 4 of 20 At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted. Table 2. AD7393 Parameter Symbol Conditions 3 V ± 10% 5 V ± 10% Unit STATIC PERFORMANCE Resolution1 N 10 10 Bits Relative Accuracy2 INL TA = +25°C ±1.75 ±1.75 LSB max TA = −40°C, +85°C, +125°C ±2.0 ±2.0 LSB max Differential Nonlinearity2 DNL Monotonic ±0.8 ±0.8 LSB max Zero-Scale Error VZSE Data = 0x000 9.0 9.0 mV max Full-Scale Voltage Error VFSE TA = +25°C, +85°C, +125°C, data = 0x3FF ±32 ±32 mV max TA = −40°C, data = 0x3FF ±42 ±42 mV max Full-Scale Temperature Coefficient3 TCVFS 28 28 ppm/°C typ REFERENCE INPUT VREF IN Range VREF 0/VDD 0/VDD V min/max Input Resistance RREF 2.5 2.5 MΩ typ4 Input Capacitance3 CREF 5 5 pF typ ANALOG OUTPUT Output Current (Source) IOUT Data = 0x200, Δ VOUT = 5 LSB 1 1 mA typ Output Current (Sink) IOUT Data = 0x200, Δ VOUT = 5 LSB 3 3 mA typ Capacitive Load3 CL No oscillation 100 100 pF typ LOGIC INPUTS Logic Input Low Voltage VIL 0.5 0.8 V max Logic Input High Voltage VIH VDD − 0.6 VDD − 0.6 V min Input Leakage Current IIL 10 10 μA max Input Capacitance3 CIL 10 10 pF max INTERFACE TIMING3, 5 Chip Select Write Width tCS 45 45 ns Data Setup tDS 30 15 ns Data Hold tDH 20 5 ns Reset Pulse Width tRS 40 30 ns AC CHARACTERISTICS Output Slew Rate SR Data = 0x000 to 0x3FF to 0x000 0.05 0.05 V/μs typ Settling Time6 tS To ±0.1% of full scale 70 60 μs typ Shutdown Recovery Time tSDR 80 μs typ DAC Glitch Code 0x7FF to Code 0x800 to Code 0x7FF 65 65 nV/s typ Digital Feedthrough 15 15 nV/s typ Feedthrough VOUT/VREF VREF = 1.5 V dc 11 V p-p, data = 0x000, f = 100 kHz −63 −63 dB typ SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max Positive Supply Current IDD VIL = 0 V, no load, TA = +25°C 55 55 μA typ VIL = 0 V, no load 100 100 μA max Shutdown Supply Current IDD-SD SHDN = 0, VIL = 0 V, no load 0.1/1.5 0.1/1.5 μA typ/max Power Dissipation PDISS VIL = 0 V, no load 300 500 μW max Power Supply Sensitivity PSS Δ VDD = ±5% 0.006 0.006 %/% max 1 One LSB = VREF/1024 V for the 10-bit AD7393. 2 The first two codes (0x000, 0x001) are excluded from the linearity error measurement. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25°C. 5 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. |
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