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AD7564BRS Datasheet(PDF) 1 Page - Analog Devices |
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AD7564BRS Datasheet(HTML) 1 Page - Analog Devices |
1 / 17 page AD7564 a FEATURES Four 12-Bit DACs in One Package 4-Quadrant Multiplication Separate References Single Supply Operation Guaranteed Specifications with +3.3 V/+5 V Supply Low Power Versatile Serial Interface Simultaneous Update Capability Reset Function 28-Pin SOIC, SSOP and DIP Packages APPLICATIONS Process Control Portable Instrumentation General Purpose Test Equipment FUNCTIONAL BLOCK DIAGRAM V A R B DAC A DAC A LATCH INPUT LATCH A INPUT LATCH B INPUT LATCH C INPUT LATCH D DAC B LATCH DAC C LATCH DAC D LATCH DAC B DAC C DAC D V B REF V D REF R D R C FB FB R A FB REF V C REF VDD DGND LDAC CLR AD7564 12 12 12 12 12 12 12 CONTROL LOGIC + INPUT SHIFT REGISTER CLKIN SDIN SDOUT 12 FSIN I A I A I B I B I C I D OUT1 OUT2 OUT1 OUT2 OUT1 FB OUT1 A0 A1 12 NC AGND I C OUT2 I D OUT2 PRODUCT HIGHLIGHTS 1. The AD7564 contains four 12-bit current output DACs with separate VREF inputs. 2. The AD7564 can be operated from a single +3.3 V to +5 V supply. 3. Simultaneous update capability and reset function are available. 4. The AD7564 features a fast, versatile serial interface com- patible with modern 3 V and 5 V microprocessors and microcomputers. 5. Low power, 50 µW at 5 V and 33 µW at 3.3 V. LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: Fax: REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. GENERAL DESCRIPTION The AD7564 contains four 12-bit DACs in one monolithic device. The DACs are standard current output with separate VREF, IOUT1, IOUT2 and RFB terminals. These DACs operate from a single +3.3 V to +5 V supply. The AD7564 is a serial input device. Data is loaded using FSIN , CLKIN and SDIN. Two address pins A0 and A1 set up a device address, and this feature may be used to simplify device loading in a multi-DAC environment. Alternatively, A0 and A1 can be ignored and the serial out capability used to configure a daisy-chained system. All DACs can be simultaneously updated using the asynchro- nous LDAC input, and they can be cleared by asserting the asynchronous CLR input. The device is packaged in 28-pin SOIC, SSOP and DIP packages. 781/329-4700 781/461-3113 B |
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