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ADRF6750ACPZ-R7 Datasheet(PDF) 9 Page - Analog Devices |
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ADRF6750ACPZ-R7 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 40 page  ADRF6750 Rev. A | Page 9 of 40 Pin No. Mnemonic Description 27 CS Chip Select, CMOS Input. When CS is high, the data stored in the shift registers is loaded into one of 31 latches. In I2C mode, when CS is high, the slave address of the device is 0x60, and when CS is low, the slave address is 0x40. 29 SDI/SDA Serial Data Input for SPI Port/Serial Data Input/Output for I2C Port. In SPI mode, this pin is a high impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a bidirec- tional port. 30 CLK/SCL Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers. This input is a high impedance CMOS input. 28 SDO Serial Data Output for SPI Port. Register states can be read back on the SDO data output line. 17 REFIN Reference Input. This high impedance CMOS input should be ac-coupled. 18 REFIN Reference Input Bar. This pin should be either grounded or ac-coupled to ground. 48 RFOUT RF Output. Single-ended, 50 Ω, internally biased RF output. This pin must be ac-coupled to the load. Nominal output power is −1.6 dBm for a single sideband baseband drive of 0.9 V p-p differ- ential on the I and Q inputs (attenuation = minimum). 45 TXDIS Output Disable. This pin can be used to disable the RF output. Connect to high logic level to disable the output. Connect to low logic level for normal operation. 25, 26 LOMONP, LOMONN Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to REGOUT. These outputs can be disabled through serial port programming and should be tied to REGOUT if not used. 22, 23 TESTLO, TESTLO Differential Test Inputs. These inputs provide an option for an external 2× LO to drive the modulator. This option can be selected by serial port programming. These inputs must be externally dc-biased and should be grounded if not used. 10, 8 LF2, LF3 No connect pins. 44 LDET Lock Detect. This output pin indicates the state of the PLL: a high level indicates a locked condition, whereas a low level indicates a loss of lock condition. 43 MUXOUT Muxout. This output is a test output for diagnostic use only. It should be left unconnected by the customer. Exposed Paddle EP Exposed Paddle. Connect to ground plane via a low impedance path. |
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