TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

POST OFFICE BOX 1443

77251–1443

4

read/output disable

When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus,

the output of any particular device in the circuit can be read with no interference from the competing outputs

of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins.

All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these

pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs.

This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices

are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup

without compromising performance or packing density.

power down

by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.

erasure (TMS27C128)

Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to

a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to

assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A

programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light

exposure dose (UV intensity

erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It

should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when

using the TMS27C128, the window should be covered with an opaque label.

initializing (TMS27PC128)

The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows

are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated

by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will

vary as a function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM is

pulsed.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (

µs) followed by a byte

verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-

µs

pulses per byte are provided before a failure is recognized.

one device can be programmed when the devices are connected in parallel. Locations can be

programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified

program inhibit

Programming may be inhibited by maintaining a high level input on the E or PGM pin.