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HD6413258F Datasheet(PDF) 6 Page - Renesas Technology Corp |
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HD6413258F Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 301 page  Section 6. Parallel Handshaking Interface ....................................................................... 113 6.1 Overview............................................................................................................................... 113 6.1.1 Features.................................................................................................................... 113 6.1.2 Block Diagram......................................................................................................... 114 6.1.3 Input and Output Pins .............................................................................................. 115 6.1.4 Register Configuration ............................................................................................ 115 6.2 Register Descriptions............................................................................................................ 115 6.2.1 Port 3 Data Direction Register (P3DDR) ................................................................ 115 6.2.2 Port 3 Data Register (P3DR) ................................................................................... 116 6.2.3 Handshake Control/Status Register (HCSR)........................................................... 116 6.3 Operation .............................................................................................................................. 118 6.3.1 Output Timing of Output Strobe Signal .................................................................. 118 6.3.2 Busy Signal Output Timing ..................................................................................... 119 6.3.3 Operation in Software Standby Mode ..................................................................... 119 6.3.4 Sample Application ................................................................................................. 120 6.3.5 Interrupts.................................................................................................................. 121 Section 7. 16-Bit Free-Running Timer..............................................................................123 7.1 Overview............................................................................................................................... 123 7.1.1 Features.................................................................................................................... 123 7.1.2 Block Diagram......................................................................................................... 123 7.1.3 Input and Output Pins .............................................................................................. 125 7.1.4 Register Configuration ............................................................................................ 125 7.2 Register Descriptions............................................................................................................ 126 7.2.1 Free-Running Counter (FRC) – H’FF92 ................................................................. 126 7.2.2 Output Compare Registers A and B (OCRA and OCRB) – H’FF94 and H’FF96............................................................ 126 7.2.3 Input Capture Register (ICR) – H’FF98.................................................................. 127 7.2.4 Timer Control Register (TCR) – H’FF90 ................................................................ 128 7.2.5 Timer Control/Status Register (TCSR) – H’FF91................................................... 130 7.2.6 FRT Noise Canceler Control Register (FNCR) – H’FFFF...................................... 133 7.3 CPU Interface ....................................................................................................................... 133 7.4 Operation .............................................................................................................................. 136 7.4.1 FRC Incrementation Timing.................................................................................... 136 7.4.2 Output Compare Timing.......................................................................................... 138 7.4.3 FRC Clear Timing ................................................................................................... 138 7.4.4 Input Capture Timing .............................................................................................. 139 7.4.5 Timing of Input Capture Flag (ICF) Setting............................................................ 140 iii |
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