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TMS320DM6467CZUT7 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320DM6467CZUT7 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 355 page  TMS320DM6467 SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 www.ti.com Table 3-1. Characteristics of the DM6467 Processor HARDWARE FEATURES DM6467 DDR2 Memory Controller DDR2 (16/32-bit bus width) 297-MHz (-594) 310.5-MHz (-729) Asynchronous (8/16-bit bus width) RAM, Flash Asynchronous EMIF (EMIFA) (NOR, NAND) 64 independent channels EDMA 8 QDMA channels 2 64-Bit General Purpose (each configurable as 2 Timers separate 32-bit timers) 1 64-Bit Watchdog 3 (with SIR, MIR, CIR support and RTS/CTS flow UART control) (UART0 Supports Modem Interface) SPI 1 (supports 2 slave devices) I2C 1 (Master/Slave) 2 (one transmit/receive with 4 serializers, Multichannel Audio Serial Port (McASP) one DIT transmit only with 1 serializer for S/PDIF output) 10/100/1000 Ethernet MAC with Management Data 1 (with MII/GMII Interface) Peripherals Input/Output (MDIO) VLYNQ 1 Not all peripherals pins are available at the same time General-Purpose Input/Output Port (GPIO) Up to 33 pins (for more detail, see the PWM 2 outputs Device Configurations section). ATA 1 (ATA/ATAPI-6) PCI 1 (32-bit, 33 MHz) HPI 1 (16-/32-bit multiplexed address/data) 1 [horizontal and vertical downscaling, VDCE chroma conversion (4:2:2 ↔4:2:0)] Clock Recovery Generator (CRGEN) 1 Power Sleep Controller (PSC) 1 (peripheral/module clock gating) 2 8-bit BT.656 capture channels or Configurable Video Port Interface (VPIF) 1 16-bit Y/C capture channel or 99-MHz (-594) 1 8-/10-/12-bit raw video capture channel and 108-MHz (-729) 2 8-bit BT.656 display channels or 1 16-bit Y/C display channel MPEG transport stream interface 1 with 8-bit parallel or serial input and output Transport Stream Interface (TSIF) 1 with serial-only input and output Each with corresponding clock recovery generator (CRGEN) for external VCXO control. High- and Full-Speed Device USB 2.0 High-, Full-, and Low-Speed Host Size (Bytes) 248KB RAM, 8KB ROM DSP • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 128KB Unified Mapped RAM/Cache (L2) On-Chip Memory Organization ARM • 16KB I-cache • 8KB D-cache • 32KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 8 Device Overview Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 |
Similar Part No. - TMS320DM6467CZUT7 |
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Similar Description - TMS320DM6467CZUT7 |
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