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TMS370C080NA Datasheet(PDF) 7 Page - Texas Instruments |
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TMS370C080NA Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 45 page  TMS370Cx8x 8-BIT MICROCONTROLLER SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 central processing unit (CPU) (continued) status register The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits. D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow. D The two interrupt-enable bits control the two interrupt levels. The ST, status-bit notation, and status-bit definitions are shown in Table 3. Table 3. Status Registers 7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset program counter (PC) The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH), and the program counter low (PCL). These registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address. During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector. Memory Program Counter (PC) 60 00 PCH PCL 60 00 0000h 7FFEh 7FFFh Figure 2. Program Counter After Reset memory map The TMS370Cx8x architecture is based on the Von Neuman architecture, in which the program memory and data memory share a common address space. All peripheral input / output is memory-mapped in this same common address space. As shown in Figure 3, the TMS370Cx8x provides memory-mapped RAM, ROM, data EEPROM, I / O pins, peripheral functions, and system-interrupt vectors. The peripheral file contains all I / O port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh and is divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is |
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