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ADS1218Y250 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS1218Y250 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 44 page  www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V ADS1218 SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 All specifications T MIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, R DAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog Input Range Buffer Off AGND – 0.1 AVDD + 0.1 V Buffer On AGND + 0.05 AVDD – 1.5 V Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±VREF/PGA V Input Impedance Buffer Off 5/PGA M Ω Input Current Buffer On 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469 × fDATA Hz –3dB 0.318 × fDATA Hz Sinc2 Filter –3dB 0.262 × fDATA Hz Sinc3 Filter Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance 9 pF Input Leakage Current Modulator Off, T = +25°C 5 pA Burnout Current Sources 2 µA OFFSET DAC Offset DAC Range ±VREF/(2 × PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±10 % Offset DAC Gain Error Drift 2 ppm/°C SYSTEM PERFORMANCE Resolution 24 Bits No Missing Codes 24 Bits Integral Nonlinearity End Point Fit ±0.0015 % of FS Offset Error(1) Before Calibration 15 ppm of FS Offset Drift(1) 0.04 ppm of FS/°C Gain Error After Calibration 0.010 % Gain Error Drift(1) 1.0 ppm/°C Common-Mode Rejection at DC 100 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output Noise See Typical Characteristics Power-Supply Rejection at DC, dB = –20 log( ∆VOUT/∆VDD)(2) 75 90 dB VOLTAGE REFERENCE INPUT Reference Input Range REF IN+, REF IN– 0 AVDD V VREF VREF ≡ (REF IN+) – (REF IN–) 0.1 1.25 V Common-Mode Rejection at DC 120 dB Common-Mode Rejection fVREFCM = 60Hz, fDATA = 60Hz 120 dB Bias Current(3) VREF = 1.25V 0.65 µA (1) Calibration can minimize these errors. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency. 5 |
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