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ADS7816U2K5 Datasheet(PDF) 9 Page - Texas Instruments

Part # ADS7816U2K5
Description  12-Bit High Speed Micro Power Sampling
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS7816U2K5 Datasheet(HTML) 9 Page - Texas Instruments

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9
®
ADS7816
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tSMPL
Analog Input Sample TIme
1.5
2.0
Clk Cycles
tCONV
Conversion Time
12
Clk Cycles
tCYC
Throughput Rate
200
kHz
tCSD
CS Falling to
0
ns
DCLOCK LOW
tSUCS
CS Falling to
30
ns
DCLOCK Rising
thDO
DCLOCK Falling to
15
ns
Current DOUT Not Valid
tdDO
DCLOCK Falling to Next
85
150
ns
DOUT Valid
tdis
CS Rising to DOUT Tri-State
25
50
ns
ten
DCLOCK Falling to DOUT
50
100
ns
Enabled
tf
DOUT Fall Time
70
100
ns
tr
DOUT Rise Time
60
100
ns
value for one clock period. For the next 12 DCLOCK
periods, DOUT will output the conversion result, most sig-
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
The reference current diminishes directly with both conver-
sion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the con-
verter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Perfor-
mance Curves section for more information.
DIGITAL INTERFACE
SERIAL INTERFACE
The ADS7816 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for DOUT is acceptable,
the system can use the falling edge of DCLOCK to capture
each bit.
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
FIGURE 1. ADS7816 Basic Timing Diagrams.
TABLE I. Timing Specifications –40
°C to +85°C.
CS/SHDN
D
OUT
DCLOCK
t
DATA
t
SUCS
t
CSD
t
CYC
t
CONV
POWER
DOWN
t
SMPL
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0(1)
NULL
BIT
HI-Z
HI-Z
B11 B10
B9
B8
NULL
BIT
CS/SHDN
D
OUT
DCLOCK
t
CONV
t
DATA
t
SUCS
t
CYC
POWER DOWN
t
SMPL
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
t
DATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
NULL
BIT
HI-Z
HI-Z
B5
B6
B7
B8
B9
B10 B11
(2)
t
CSD


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