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BQ24295RGER Datasheet(PDF) 35 Page - Texas Instruments |
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BQ24295RGER Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 45 page  1 7 Slave Address S 1 1 ACK 8 Reg Addr ACK 1 0 8 Slave Address 1 ACK 8 Data to Addr+1 ACK 1 8 Data to Addr+1 ACK 1 P 1 1 7 Slave Address S 1 1 ACK 8 Reg Addr ACK 1 ACK 1 1 P 7 0 1 Data NCK 8 Slave Address 1 1 1 S 1 7 Slave Address S 1 1 ACK 8 Reg Addr ACK 1 Data Addr ACK 1 1 P 8 0 START SCL SDA S 1-7 8 9 ACK 1-7 8 9 ACK 1-7 8 9 STOP P ADDRESS R/W DATA ACK DATA bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Acknowledge (ACK) and Not Acknowledge (NACK) The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. Slave Address and Data Direction Bit After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). Figure 35. Complete Data Transfer Single Read and Write Figure 36. Single Write Figure 37. Single Read If the register address is not defined, the charger IC send back NACK and go back to the idle state. Multi-Read and Multi-Write The charger device supports multi-read and multi-write on REG00 through REG08. Figure 38. Multi-Write Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: bq24295 |
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