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A

A

S

1

1

1

0

A2 A1

A0

0

Start Condition

SDA

R/W

ACK From Slave

ACK From Slave

P

B0

B1

B2

B3

B4

B5

B6

B7

Stop Condition

Slave Address

Control Register

Reads

A

S

1

1

1

0

A2 A1

A0

1

SDA

P

B3

B2

B1 B0

Start Condition

R/W

ACK From Slave

NACK From Master

Stop Condition

Slave Address

Control Register

B7

B6 B5

B4

NA

PCA9548A

WITH RESET

SCPS143C – OCTOBER 2006 – REVISED JUNE 2007

Figure 7. Write to Control Register

The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 4 for device

address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.

After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the

SCn/SDn channel defined by the command byte then is sent by the PCA9548A (see Figure 8). After a restart,

the value of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed

when the restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse.

There is no limitation on the number of data bytes received in one read transmission, but when the final byte is

received, the bus master must not acknowledge the data.

Figure 8. Read From Control Register

9

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