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EPM3128A Datasheet(PDF) 32 Page - Altera Corporation |
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EPM3128A Datasheet(HTML) 32 Page - Altera Corporation |
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32 / 46 page  32 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet tCLR Register clear time 1.3 2.1 2.9 ns tPIA PIA delay (2) 1.0 1.7 2.3 ns tLPA Low–power adder (5) 3.5 4.0 5.0 ns Table 20. EPM3128A External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit –5 –7 –10 Min Max Min Max Min Max tPD1 Input to non– registered output C1 = 35 pF (2) 5.0 7.5 10 ns tPD2 I/O input to non– registered output C1 = 35 pF (2) 5.0 7.5 10 ns tSU Global clock setup time (2) 3.3 4.9 6.6 ns tH Global clock hold time (2) 0.0 0.0 0.0 ns tCO1 Global clock to output delay C1 = 35 pF 1.0 3.4 1.0 5.0 1.0 6.6 ns tCH Global clock high time 2.0 3.0 4.0 ns tCL Global clock low time 2.0 3.0 4.0 ns tASU Array clock setup time (2) 1.8 2.8 3.8 ns tAH Array clock hold time (2) 0.2 0.3 0.4 ns tACO1 Array clock to output delay C1 = 35 pF (2) 1.0 4.9 1.0 7.1 1.0 9.4 ns tACH Array clock high time 2.0 3.0 4.0 ns tACL Array clock low time 2.0 3.0 4.0 ns tCPPW Minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns tCNT Minimum global clock period (2) 5.2 7.7 10.2 ns fCNT Maximum internal global clock frequency (2), (4) 192.3 129.9 98.0 MHz tACNT Minimum array clock period (2) 5.2 7.7 10.2 ns Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit –4 –7 –10 Min Max Min Max Min Max |
Similar Part No. - EPM3128A |
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Similar Description - EPM3128A |
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