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AD7890SQ-10QML Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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AD7890SQ-10QML Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 17 page  STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/, 3/, 5/ -55 °C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Master clock frequency 6/ fCLKIN 9, 10, 11 01 0.1 2.5 MHz Master clock input low time tCLKINL 9, 10, 11 01 0.3 x tCLKIN ns Master clock input high time tCLKINH 9, 10, 11 01 0.3 x tCLKIN ns Digital output rise time 7/ tR 9, 10, 11 01 25 ns Digital output fall time 7/ tF 9, 10, 11 01 25 ns Conversion time tCONVERT 9, 10, 11 01 5.9 µs CONVST pulse width tCST 9, 10, 11 01 100 ns RFS low to SCLK falling edge t1 9, 10, 11 01 tCLKINH + 50 ns RFS low to valid delay 8/ t2 9, 10, 11 01 25 ns SCLK high pulse width t3 9, 10, 11 01 tCLKINH ns SCLK low pulse width t4 9, 10, 11 01 tCLKINL ns SCLK rising edge to data valid delay 8/ t5 9, 10, 11 01 20 ns SCLK rising edge to RFS delay t6 9, 10, 11 01 40 ns Bus relinquish time after rising edge of SCLK 9/ t7 9, 10, 11 01 50 ns TFS low to SCLK falling edge t8 9, 10, 11 01 0 tCLKIN + 50 ns Data valid to TFS falling edge setup time (A2 address bit) t9 9, 10, 11 01 0 ns Data valid to SCLK falling edge setup time t10 9, 10, 11 01 20 ns See footnotes at end of table. |
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