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SN65HVD10DRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVD10DRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 28 page SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11 SN65HVD12, SN75HVD12 SLLS505M – FEBRUARY 2002 – REVISED JULY 2013 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output HVD10 12.5 20 25 ns tPHL Propagation delay time, high-to-low-level output HVD10 12.5 20 25 HVD11 tPLH Propagation delay time, low-to-high-level output 30 55 70 ns HVD12 VID = –1.5 V to 1.5 V, HVD11 CL = 15 pF, tPHL Propagation delay time, high-to-low-level output 30 55 70 ns HVD12 See Figure 8 HVD10 1.5 tsk(p) Pulse skew (|tPHL – tPLH|) HVD11 4 ns HVD12 4 HVD10 8 tsk(pp) (2) Part-to-part skew HVD11 15 ns HVD12 15 tr Output signal rise time 1 2 5 CL = 15 pF, ns See Figure 8 tf Output signal fall time 1 2 5 tPZH (1) Output enable time to high level 15 tPZL (1) Output enable time to low level 15 CL = 15 pF, DE at 3 V, ns See Figure 9 tPHZ Output disable time from high level 20 tPLZ Output disable time from low level 15 tPZH (2) Propagation delay time, standby-to-high-level output 6 CL = 15 pF, DE at 0, μs See Figure 10 tPZL (2) Propagation delay time, standby-to-low-level output 6 (1) All typical values are at 25°C and with a 3.3-V supply (2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. THERMAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High −K board(3), No airflow D pkg 121 Junction −to−ambient thermal θJA resistance(2) No airflow(4) P pkg 93 High −K board D pkg 67 Junction −to−board thermal θJB °C/W resistance See (4) P pkg 57 D pkg 41 Junction −to−case thermal θJC resistance P pkg 55 HVD10 198 250 (32 Mbps) RL= 60 Ω, CL = 50 pF, DE at VCC, RE at 0 V, HVD11 141 176 PD Device power dissipation mW Input to D a 50% duty cycle square (10 Mbps) wave at indicated signaling rate HVD12 133 161 (500 kbps) High −K board, No airflow D pkg –40 116 TA Ambient air temperature No airflow(4) P pkg –40 123 °C TJSD Thermal shutdown junction temperature 165 (1) See Application Information section for an explanation of these parameters. (2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. (3) JSD51 −7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. (4) JESD51 −10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements. 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD11Q SN75HVD11 SN65HVD12 SN75HVD12 |
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