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TLC5618ACD Datasheet(PDF) 7 Page - Texas Instruments |
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TLC5618ACD Datasheet(HTML) 7 Page - Texas Instruments |
7 / 24 page TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS156G – JULY 1997 – REVISED APRIL 2001 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref(REFIN) = 2.048 V (unless otherwise noted) (continued) digital input timing requirements MIN NOM MAX UNIT t (DS) Setup time DIN before SCLK low C and I suffixes 5 ns tsu(DS) Setup time, DIN before SCLK low Q and M suffixes 8 ns th(DH) Hold time, DIN valid after SCLK low 5 ns tsu(CSS) Setup time, CS low to SCLK low 5 ns tsu(CS1) Setup time, SCLK ↑ to CS ↑, external end-of-write 10 ns tsu(CS2) Setup time, SCLK ↑ to CS ↓, start of next write cycle 5† ns tw(CL) Pulse duration, SCLK low 25 ns tw(CH) Pulse duration, SCLK high 25 ns † Not production tested for Q and M suffixes. NOTE A: SCLK must go high after the 16th falling clock edge. tsu(CSS) tw(CL) tw(CH) CS SCLK DIN tsu(DS) th(DH) D15 D14 D13 D12 D11 D0 ts DAC A/B OUT ≤ Final Value ±0.5 LSB (see Note A) Program Bits (4) DAC Data Bits (12) tsu(CS1) tsu(CS2) Figure 1. Timing Diagram for the TLC5618A |
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