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TMS320TCI6482GTZ Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320TCI6482GTZ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 260 page  TMS320TCI6482 www.ti.com SPRS246K – APRIL 2005 – REVISED MARCH 2012 TMS320TCI6482 Communications Infrastructure Digital Signal Processor Check for Samples: TMS320TCI6482 1 Features 12 (FPGA, CPLD, ASICs, etc.) • High-Performance Communications Infrastructure DSP (TCI6482) – 32M-Byte Total Addressable External Memory Space – 1.17-, 1-, and 0.83-ns Instruction Cycle Time • Four 1x Serial RapidIO® Links (or One 4x), – 850-MHz, 1-GHz, and 1.2-GHz Clock Rate v1.2 Compliant – Eight 32-Bit Instructions/Cycle – 1.25-, 2.5-, 3.125-Gbps Link Rates – 9600 MIPS/MMACS (16-Bits) – Message Passing, DirectIO Support, Error – Commercial Temperature [0°C to 90°C] Mgmt Extensions, Congestion Control – Extended Temperature [-40°C to 105°C] – IEEE 1149.6 Compliant I/Os • TMS320C64x+™ DSP Core • DDR2 Memory Controller – Dedicated SPLOOP Instruction – Interfaces to DDR2-533 SDRAM – Compact Instructions (16-Bit) – 32-Bit/16-Bit, 533-MHz (data rate) Bus – Instruction Set Enhancements – 512M-Byte Total Addressable External – Exception Handling Memory Space • TMS320C64x+ Megamodule L1/L2 Memory • EDMA3 Controller (64 Independent Channels) Architecture: • 32-/16-Bit Host-Port Interface (HPI) – 256K-Bit (32K-Byte) L1P Program Cache • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component [Direct Mapped] Interconnect (PCI) Master/Slave Interface – 256K-Bit (32K-Byte) L1D Data Cache Conforms to PCI Local Bus Specification (v2.3) [2-Way Set-Associative] • One Inter-Integrated Circuit (I2C) Bus – 16M-Bit (2048K-Byte) L2 Unified Mapped • Two McBSPs RAM/Cache [Flexible Allocation] • 10/100/1000 Mb/s Ethernet MAC (EMAC) – 256K-Bit (32K-Byte) L2 ROM – IEEE 802.3 Compliant – Time Stamp Counter – Supports Multiple Media Independent • 2 RSAs for CDMA Processing Interfaces (MII, GMII, RMII, and RGMII) – Dedicated RAKE, PATH_SEARCH and – 8 Independent Transmit (TX) and RACH_SEARCH Instructions 8 Independent Receive (RX) Channels – Transmit Processing Capability • Two 64-Bit General-Purpose Timers, • Enhanced Viterbi Decoder Coprocessor (VCP2) Configurable as Four 32-Bit Timers – Supports Over 694 7.95-Kbps AMR • UTOPIA – Programmable Code Parameters – UTOPIA Level 2 Slave ATM Controller • Enhanced Turbo Decoder Coprocessor (TCP2) – 8-Bit Transmit and Receive Operations up to – Supports up to Eight 2-Mbps 3GPP 50 MHz per Direction (6 Iterations) – User-Defined Cell Format up to 64 Bytes – Programmable Turbo Code and Decoding • VLYNQ™ Port Parameters – Full Duplex Serial Bus • Endianess: Little Endian, Big Endian – Up to 4-Bit Transmit, 4-Bit Receive • 64-Bit External Memory Interface (EMIFA) – Up to 125-MHz Operation – Glueless Interface to Asynchronous • 16 General-Purpose I/O (GPIO) Pins Memories (SRAM, Flash, and EEPROM) and • System PLL and PLL Controller Synchronous Memories (SBSRAM, ZBT SRAM) • Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller – Supports Interface to Standard Sync Devices and Custom Logic • Advanced Event Triggering (AET) Compatible 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2005–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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