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SN74CBT16232DLRG4 Datasheet(PDF) 3 Page - Texas Instruments

Part # SN74CBT16232DLRG4
Description  SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74CBT16232DLRG4 Datasheet(HTML) 3 Page - Texas Instruments

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Recommended Operating Conditions
(1)
Electrical Characteristics
Timing Requirements
SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009N – MAY 1995 – REVISED JUNE 2007
MIN
MAX
UNIT
VCC
Supply voltage
4
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
TA
Operating free-air temperature
–40
85
°C
(1)
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIK
VCC = 4.5 V,
II = –18 mA
–1.2
V
II
VCC = 5.5 V,
VI = 5.5 V or GND
±1
μA
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
3
μA
Control
Other inputs at VCC or
ΔICC
(2)
VCC = 5.5 V,
One input at 3.4 V,
2.5
mA
inputs
GND
Control
CI
VI = 3 V or 0
4.5
pF
inputs
A port
6.5
Cio(OFF)
VO = 3 V or 0,
CLKEN = 0,
S0 and S1 = GND
pF
B port
4
VCC = 4 V,
VI = 2.4 V,
II = 15 mA
14
20
TYP at VCC = 4 V
II = 64 mA
5
7
ron
(3)
VI = 0
VCC = 4.5 V
II = 30 mA
5
7
VI = 2.4 V,
II = 15 mA
10
15
(1)
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
(2)
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
(3)
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
over recommended operating free-air temperature range (unless otherwise noted)
VCC = 5 V
VCC = 4 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
MHz
tw
Pulse duration
CLK high or low
3.3
3.3
ns
S0, S1 before CLK
2.2
1.9
tsu
Setup time
ns
CLKEN before CLK
2.4
1.9
S0, S1 after CLK
0.5
1
th
Hold time
ns
CLKEN after CLK
1.9
1.8
3
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