OUTA

12/10/8

12/10/8

Band-Gap

Voltage

2

Serial

Interface

12

8

REF

SCLK

DIN

FS

MODE

DOUT

DAC B, C, D, E, F, G and H

Same as DAC A

OUT

1 V or 2 V

PRE

LDAC

(Trimmed)

with Enable

X2

B, C, D,

E, F, G

and H

DAC A

Holding

Latch

DAC A

Latch

12/10/8

TLV5630

TLV5631

TLV5632

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

SOIC (DW)

TSSOP (PW)

RESOLUTION

TLV5630IDW

TLV5630IPW

12

40°C to 85°C

TLV5631IDW

TLV5631IPW

10

TLV5632IDW

TLV5632IPW

8

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AGND

10

P

Analog ground

11

P

Analog power supply

DGND

1

P

Digital ground

DIN

2

I

Digital serial data input

DOUT

19

O

Digital serial data output

20

P

Digital power supply

FS

4

I

Frame sync input

LDAC

18

I

Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.

MODE

17

I

DSP/

µC mode pin. High = µC mode, NC = DSP mode.

PRE

5

I

Preset input

REF

16

I/O

Voltage reference input/output

SCLK

3

I

Serial clock input

OUTA-OUTH

12-15, 6-9

O

DAC outputs A, B, C, D, E, F, G and H

2

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