FAN54042 datasheet(7/41 Pages) FAIRCHILD

Part #	FAN54042

Description	USB-OTG, 1.55 A, Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

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Manufacturer	FAIRCHILD [Fairchild Semiconductor]

Direct Link	http://www.fairchildsemi.com

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FAN54040

– FAN54047 • Rev. 1.0.2

7

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25°C.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Input Power Source Detection

T1

T1 (0°C) Temperature Threshold

71.9

73.9

75.9

% of

VREF

T2

T1 (10°C) Temperature Threshold

62.6

64.6

66.6

T3

T1 (45°C) Temperature Threshold

31.9

32.9

34.9

T4

T1 (60°C) Temperature Threshold

21.3

23.3

25.3

Input Power Source Detection

VIN(MIN)1

VBUS Input Voltage Rising

To Initiate and Pass VBUS Validation

4.29

4.42

V

VIN(MIN)2

Minimum VBUS during Charge

During Charging

3.71

3.94

V

tVBUS_VALID

VBUS Validation Time

30

ms

VBUS Control Loop

VBUSLIM

VBUS Loop Setpoint Accuracy

–3

+3

%

Input Current Limit

IBUSLIM

Charger Input Current Limit

Threshold

IBUSLIM Set to 100 mA

88

93

98

mA

IBUSLIM Set to 500 mA

450

475

500

VREF Bias Generator

VREF

Bias Regulator Voltage

VBUS > VIN(MIN)

1.8

V

Short-Circuit Current Limit

2.5

mA

Battery Recharge Threshold

VRCH

Recharge Threshold

Below V(OREG)

100

120

150

mV



Deglitch Time

VBAT Falling Below VRCH Threshold

130

ms

STAT, POK_B Output

VSTAT(OL)

STAT Output Low

ISTAT=10 mA

0.4

V



ISTAT(OH)

STAT High Leakage Current

VSTAT=5 V

1

A

Battery Detection

IDETECT

Battery Detection Current before

Charge Done (Sink Current)

(5)

Begins after Termination Detected

and VBAT < VOREG –VRCH

–0.8

mA

tDETECT

Battery Detection Time

262

ms

Sleep Comparator

VSLP

Sleep-Mode Entry Threshold,

VBUS – VBAT

2.3 V < VBAT < VOREG, VBUS Falling

0

0.04

0.10

V

Power Switches (see Figure 2)

RDS(ON)

Q3 On Resistance (VBUS to PMID)

IIN(LIMIT)=500 mA

180

250

m

Ω



Q1 On Resistance (PMID to SW)

130

225

Q2 On Resistance (SW to GND)

150

225

Q4 On Resistance (SYS to VBAT)

VBAT=4.2 V

70

100

m

Ω



ISYNC

Synchronous to Non-Synchronous

Current Cut-Off Threshold

(6)

Low-Side MOSFET (Q2) Cycle-by-

Cycle Current Limit

140

mA

Continued on the following page…

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