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TPS62240DRVTG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS62240DRVTG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 29 page www.ti.com PIN ASSIGNMENTS V IN GND EN SW FB 1 2 3 5 4 DDCPACKAGE (TOP VIEW) DRV PACKAGE (TOPVIEW) MODE FB GND SW EN VIN 1 2 3 6 5 4 r Po w e P A D Zero-Pole AMP. Integrator Error Amp . PFMComparator PWM Comp. VREF Control Stage GateDriver Anti- Shoot-Through Current LimitComparator Current LimitComparator VREF FB FB VIN GND MODE 2.25 MHz Oscillator SW1 EN VIN Softstart VOUT RAMP CONTROL Thermal Shutdown Reference 0.6VVREF Undervoltage Lockout 1.8V Limit HighSide Limit LowSide Sawtooth Generator Int. Resistor Network FB RI 1 RI..N Mode Onlyin 2x2SON GND TPS62240, TPS62242, TPS62243 SLVS762B – JUNE 2007 – REVISED SEPTEMBER 2007 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NO. NO. NAME (SON) TSTO23-5 VIN 5 1 PWR VIN power supply pin. GND 6 2 PWR GND supply pin This is the enable pin of the device. Pulling this pin to low forces the device into shutdown EN 4 3 I mode. Pulling this pin to high enables the device. This pin must be terminated. This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor SW 1 5 OUT to this terminal. Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. FB 3 4 I In case of fixed output voltage option, connect this pin directly to the output capacitor. This pin is only available at SON package option. MODE pin = high forces the device to MODE 2 I operate in fixed frequency PWM mode. MODE pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed frequency PWM mode. FUNCTIONAL BLOCK DIAGRAM 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS62240 TPS62242 TPS62243 |
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