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TMS320C6670CYPA2 Datasheet(PDF) 17 Page - Texas Instruments |
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TMS320C6670CYPA2 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 226 page  Multicore Fixed and Floating-Point System-on-Chip Copyright 2012 Texas Instruments Incorporated Device Overview 17 SPRS689D—March 2012 TMS320C6670 www.ti.com Submit Documentation Feedback 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the TMS320C6670 SoC. The table shows the significant features of the device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1 Characteristics of the C6670 SoC (Part 1 of 2) Hardware Features TMS320C6670 Peripherals DDR3 memory controller (64-bit bus width) [1.5-V I/O] (clock source = DDRREFCLKN|P) 1 EDMA3 (16 independent channels) [CPU/2 clock rate] 1 EDMA3 (64 independent channels) [CPU/3 clock rate] 2 High-speed 1×/2×/4× Serial RapidIO port (4 lanes) 1 Second-generation Antenna Interface (AIF2) 1 I 2C 1 SPI 1 PCIe (2 lanes) 1 UART 1 10/100/1000 Ethernet 2 Management Data Input/Output (MDIO) 1 64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) Eight 64-bit or Sixteen 32-bit General-Purpose Input/Output Port (GPIO) 16 Encoder/Decoder Coprocessors VCP2 (clock source = CPU/3 clock frequency) 4 TCP3d (clock source = CPU/2 clock frequency) 3 TCP3e (clock source = CPU/3 clock frequency) 1 FFTC (clock source = CPU/3 clock frequency) 3 BCP (clock source = CPU/3 clock frequency) 1 Accelerators Receive Accelerator (RAC) 2 Transmit Accelerator (TAC) 1 Rake/Search Accelerator (RSA) 4 Packet Accelerator (PA) 1 Security Accelerator (1) (SA) 1 On-Chip Memory Size (Bytes) 6528K Organization 128KB L1 Program Memory Controller [SRAM/Cache] 128KB L1 Data Memory Controller [SRAM/Cache] 4096KB L2 Unified Memory/Cache 2048KB MSM SRAM 128KB L3 ROM C66x CorePac Revision ID CorePac Revision ID Register (address location: 0181 2000h) See Section 5.5 ‘‘CorePac Revision’’ on page 104. JTAG BSDL_ID JTAGID register (address location: 0x02620018) See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register Description’’ on page 73 Frequency MHz 1200 (1.2 GHz) [-1200] 1000 (1.0 GHz) [-1000] Cycle Time ns 0.83 ns [-1200] 1 ns [-1000] Voltage Core (V) SmartReflex variable supply I/O (V) 1.0 V, 1.5 V, and 1.8 V |
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