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TPS65580PWP Datasheet(PDF) 8 Page - Texas Instruments |
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TPS65580PWP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page TPS65580 SLVSC29 – SEPTEMBER 2013 www.ti.com OVERVIEW The TPS65580 is a 1.5A/2.5A/1.5A triple synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient response of Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS65580 is a fixed switching frequency pulse width modulation (PWM) controller that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines constant switching frequency with an internal compensation circuit and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. PWM Frequency and Adaptive On-Time Control TPS65580 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The TPS65580 runs with fixed frequency of 700 kHz. Soft Start and Pre-Biased Soft Start The TPS65580 has an internal, 1.2ms, soft-start for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. The TPS65580 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.. Current Protection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit and using HICCUP mode over current rotection. The switch current is monitored by measuring the low-side FET switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the on- resistance of the FET. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iox. If the sensed voltage on the low side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is monitored in the same manner. Following are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. When the over current condition is removed, the output voltage returns to the regulated value. This protection is non-latching. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65580 |
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