BQ77910ADBTR datasheet(7/52 Pages) TI1

Part #	BQ77910ADBTR

Description	Multi-Cell Lithium-Ion/Polymer Precision Protector

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Manufacturer	TI1 [Texas Instruments]

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bq77910A

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SLUSAV6

– FEBRUARY 2012

ELECTRICAL CHARACTERISTICS

Vcell(n) = 1.4 to 4.375 for all cells, TA = –25°C to 85ºC, BAT = 5.6 to 43.75 V; Typical values stated where TA = 25°C and

BAT = 36 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

CHG, DSG = on (no dc load), VREG = on,

ICC

Normal-mode average supply current

50

75

µA

IREG = 0 mA, BAT = 36 V

Vcell

< Vuv, VREG = off (EEPROM set), CPCKN = 0.3 V

5

17

ISHUTDOWN_2

(1)

Shutdown mode, LDO off

µA

Vcell

< Vuv, VREG = off (EEPROM set), CPCKN = 0.5 V

20

60

INTERNAL POWER CONTROL (STARTUP, SHUTDOWN, GATE DRIVE UNDERVOLTAGE)

VSTARTUP

Minimum voltage for initial power up

(2)

Measured at BAT pin

7

V

LDO POR voltage

– voltage on LDO that

VPOR

(3)

ILDO = 2 mA

2.7

3.2

V

initiates a POR

VGATE_UV

FET gate shutdown threshold (voltage falling)

Measured at CCAP/DCAP pins

4.5

4.9

5.3

V

VGATE_UV_H

FET gate shutdown hysteresis voltage

Measured at CCAP/DCAP pins

0.45

0.7

V

FET DRIVE

(4)

BAT voltage = 43.75 V (gate-drive circuit in regulation

11

12

14

mode), no dc load

Gate drive voltage at DSG and CHG pins for

BAT voltage = 10 V (gate-drive circuit in dropout mode), no

V(FETON)

9

V

FET ON (enabled) conditions

dc load

BAT voltage = 6.4 V (gate-drive circuit in dropout mode), no

>VGATE_UV

dc load

VO(FETOFFDSG) = V(DSG) – VGND

0.2

Gate drive voltage at DSG and CHG pins for

V(FETOFF)

V

FET OFF (disabled) conditions

VO(FETOFFCHG) = V(VHG) – Vpack–

0.2

VDSG: 10% to 90%

90

140

CL = 50 nF, BAT = 43.75 V

VCHG: 10% to 90%

90

140

tr

Rise time, measured at IC pin (CHG or DSG)

µs

VDSG: 10% to 90%

90

140

CL = 50 nF, BAT = 6.4 V

VCHG: 10% to 90%

90

140

VDSG : 90% to 10%

10

20

CL = 50 nF, BAT = 43.75 V

VCHG: 90% to 10%

20

40

tf

Fall time, measured at IC pin (CHG or DSG)

µs

VDSG : 90% to 10%

50

100

CL = 50 nF, BAT = 6.4 V

VCHG: 90% to 10%

50

100

VREG, INTEGRATED 3.3-V LDO

IOUT = 10 mA (maximum dc load)

(5)

3.1

3.3

3.55

V

Output-voltage regulation under all line, load,

VREG

temperature conditions

IOUT = 0.2 mA

3.1

3.3

3.55

V

ISC

Short-circuit current limit

VREG = 0 V, forced external short (thermally protected)

(6)

20

45

mA

(1)

For predictable shutdown current, the voltage at CPCKN with respect to VSS must be controlled. In the parallel FET case, CPCKN is

clamped through the body diode of the charge FET. In the series FET case, external circuitry is required to keep CPCKN from floating.

Contact TI for recommended application circuits.

(2)

At this voltage, the LDO has sufficient voltage to maintain regulation. The POR then enables the charger-detect logic. Logic is held in

reset until inserted into charger and LDO has reached VPOR. The part still operates below 7 V to the spec limit of 5.6 V.

(3)

VPOR and VREG are derived from the same internal reference, so that the MAX value of VPOR and the MIN value of VREG do not occur

at the same time.

(4)

FET drive is disabled if voltage at CCAP or DCAP pins

< VGATE_UV. Turnoff due to gate-drive undervoltage condition meets the same

timing requirements as logic-initiated gate turnoff.

(5)

ELECTRICAL CHARACTERISTICS assume that IOUT = 0 so that the internal junction temperature (TJ) is effectively equal to the

ambient temperature (TA). For larger non-zero values of IOUT, TJ can be significantly higher than TA. In these cases, TJ should be

substituted for TA in the test and operating conditions. TJ can be calculated from the device power dissipation as described under

THERMAL CHARACTERISTICS. The device power dissipation due to IOUT is (VBAT – VREG) × IOUT.

(6)

Regulator shuts down prior to current-limit maximum specification if junction temperature exceeds safe range.

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