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TPS40130RHBTG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS40130RHBTG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 39 page www.ti.com SIMPLIFIED APPLICATION DIAGRAM 1 2 3 4 30 29 28 27 PGND LDRV2 SW2 HDRV2 LDRV1 VIN5 SW1 HDRV1 TPS40130DBT 5 6 7 8 BOOT1 OVSET VOUT GSNS 9 10 11 DIFFO CS1 CSRT1 12 13 14 15 COMP VREF DROOP FB 26 25 24 23 BOOT2 SS UVLO BP5 22 21 20 19 AGND CS2 CSRT2 RT 18 17 16 PGOOD ILIM EN/SYNC 5 V 5 V 5 V DIFFO LOAD UDG−04017 VOUT VIN VIN VIN VREF VOUT TPS40130 SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback |
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