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M68000PM Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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M68000PM Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 14 page QUICC ARCHITECTURE OVERVIEW The QUICC is 32-bit controller that is an extension of other members of the Freescale M68300 family. Like other members of the M68300 family, the QUICC incorporates the intermodule bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB provides a common interface for all modules of the M68300 family, which allows Freescale to develop new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure 1. EXTERNAL BUS INTERFACE SYSTEM PROTECTION SIM 60 CPU32+ CORE IMB (32 BIT) RISC CONTROLLER SYSTEM I/F 2.5-KBYTE DUAL-PORT RAM DRAM CONTROLLER AND CHIP SELECTS CPM PERIODIC TIMER CLOCK GENERATION OTHER FEATURES BREAKPOINT LOGIC JTAG COMMUNICATIONS PROCESSOR FOUR GENERAL- PURPOSE TIMERS INTERRUPT CONTROLLER OTHER FEATURES TIMER SLOT ASSIGNER SEVEN SERIAL CHANNELS TWO IDMAs FOURTEEN SERIAL DMAs Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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Similar Description - M68000PM |
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