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SPT7610 Datasheet(PDF) 6 Page - Fairchild Semiconductor |
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SPT7610 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 / 10 page 6 1/21/02 SPT7610 TYPICAL INTERFACE CIRCUIT The typical interface circuit is shown in figure 3. External reference taps are provided for correcting integral nonlinearity errors. These taps can be actively driven to reduce these errors. (See the Reference Inputs discus- sion below.) The SPT7610 evaluation board application note contains more details on interfacing the SPT7610. The function of each pin and external connections to other components is as follows: POWER SUPPLY PINS: AVEE, AGND, DGND AVEE is the supply pin with AGND as ground for the de- vice. The AVEE power supply pin should be bypassed as close to the device as possible with a 10 µF tantalum ca- pacitor, in parallel with 100 pF and .01 µF chip capacitors. Place the 100 pF chip capacitor closest to the SPT7610. Digital ground (DGND) is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 3. ANALOG INPUT: VIN There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7610 is superior to similar de- vices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. CLOCK INPUTS: CLK, NCLK The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. Figure 3 – Typical Interface Circuit VIN VIN VRTF VRTS * U1 + * U1 5.2 V 2N2907 VRBS VRBF 50 W VIN 2.0 V Reference Convert 2 V Pulldown (Analog) CLK NCLK VRM R R 5.2 V * FB = Ferrite bead U1 = TLV2464 or equivalent with low offset/noise. R = 1 kW; 0.05% matched or better = AGND = DGND U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver. * = 2.2 µF Tantalum Capacitor, 0.1 µF and 100 pF chip capacitors. ** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. U2 DRB (DATA READY) DRB (DATA READY) DRA (DATA READY) DRA (DATA READY) DRB DRA DRB DRA ** FB * VR3 * VR1 D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) 2.0 V Pulldown (Digital) .1 µF D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) Test LINV MINV 5.2 V 5.2 V 5.2 V SPT7610 50 W 5.2 V 22 W 22 W 50 W |
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Similar Description - SPT7610 |
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