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SPT7734

Figure 2 - Ladder Force/Sense Circuit

AGND

VRHF

VRHS

VRLS

VRLF

VIN

1

2

3

5

6

7

+

-

All capacitors are 0.01 µF

4

N/C

Figure 3 - Simplified Reference Ladder Drive Circuit

Without Force/Sense Circuit

R/2

R

R

R

R

R

R

R/2

R=30

Ω (typ)

All capacitors are 0.01 µF

VRLF (AGND)

0.0 V

VRLS

(0.075 V)

VRHS

(+3.91 V)

90 mV

75 mV

+4.0 V

External

Reference

In cases where wider variations in offset and gain can be

sense lines to AGND with a .01

µF capacitor (chip cap

preferred) to minimize high-frequency noise injection. If this

simplified configuration is used, the following considerations

should be taken into account:

The reference ladder circuit shown in figure 3 is a simplified

representation of the actual reference ladder with force and

sense taps shown. Due to the actual internal structure of the

equal:

Figure 3 shows an example of expected voltage drops for a

ANALOG INPUT

respect to the voltage reference. (See voltage reference

section.)

The drive requirements for the analog inputs are very minimal

when compared to most other converters due to the SPT7734's

extremely low input capacitance of only 5 pF and very high

input resistance in excess of 50 k

Ω.

The analog input should be protected through a series

resistor and diode clamping circuit as shown in figure 4.

CALIBRATION

The SPT7734 uses an auto calibration scheme to en-

sure 8-bit accuracy over time and temperature. Gain and

offset errors are continually adjusted to 8-bit accuracy during

device operation. This process is completely transparent to

the user.

Upon power-up, the SPT7734 begins its calibration algo-

rithm. In order to achieve the calibration accuracy required,

the offset and gain adjustment step size is a fraction of a 8-

bit LSB. Since the calibration algorithm is an oversampling

process, a minimum of 10,000 clock cycles are required.

This results in a minimum calibration time upon power-up

of 250

µsec (for a 40 MHz clock). Once calibrated, the

SPT7734 remains calibrated over time and temperature.

Since the calibration cycles are initiated on the rising edge of

the clock, the clock must be continuously applied for the

SPT7734 to remain in calibration.

INPUT PROTECTION

All I/O pads are protected with an on-chip protection circuit

shown in figure 5. This circuit provides ESD robustness to

3.5 kV and prevents latch-up under severe discharge condi-

tions without degrading analog transition times.