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TMS320DM640GNZ400 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320DM640GNZ400 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 179 page  Tables 10 June 2003 − Revised October 2010 SPRS222F List of Tables Table Page 1−1 Characteristics of the DM641 Processor 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 Characteristics of the DM640 Processor 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 Peripherals Available on the DM641 and DM640 Devices 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 L2 Cache Registers (C64x) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 TMS320DM641/DM640 Memory Map Summary 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 Terminal Functions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 MAC_EN Peripheral Selection (EMAC and MDIO) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and TOUT0/MAC_EN) 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions 70 . . . . . . . . . . . . . . . . . . . . . . . . 2−4 PCFGLOCK Register Selection Bit Descriptions − Read Accesses 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5 PCFGLOCK Register Selection Bit Descriptions − Write Accesses 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6 Device Status (DEVSTAT) Register Selection Bit Descriptions 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7 DM641/DM640 Device Multiplexed Pin Configurations 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 Board-Level Timing Example 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 Characteristics of the Power-Down Modes 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3 TMS320DM641/DM640 EDMA Channel Synchronization Events 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4 EDMA Registers (C64x) 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 Quick DMA (QDMA) and Pseudo Registers 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 EDMA Parameter RAM (C64x) 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 DM641/DM640 DSP Interrupts 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8 Interrupt Selector Registers (C64x) 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 Timing Requirements for External Interrupts 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 Timing Requirements for Reset 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 Switching Characteristics Over Recommended Operating Conditions During Reset 97 . . . . . . . . . . . . . . 4−12 TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13 Timing Requirements for CLKIN for −400 Devices 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14 Timing Requirements for CLKIN for −500 Devices 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15 Timing Requirements for CLKIN for −600 Devices 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−16 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 102 . . . . . . . . . . . . . 4−17 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 103 . . . . . . . . . . . . . 4−18 Timing Requirements for AECLKIN for EMIFA 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−19 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−21 EMIFA Registers 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−22 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 106 . . . . . . . . . . . . . . . . . . . . 4−23 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module 109 . . . . . . . 4−25 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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